1. Field of the Invention
The invention relates to a method for forming interconnect structures, and more particularly to a method for forming interconnect structures with a low dielectric constant.
2. Description of the Prior Art
It is the nature of semiconductor physics that as the feature sizes are scaled down, the performance of internal devices in integrated circuits improves in a compounded fashion. That is, the device speed as well as the functional capability improves. The overall circuit speed, however, becomes more dependent upon the propagation speed of the signals along interconnects that connect the various devices together. With the advent of very and ultra large scale integration (VLSI and ULSI) circuits, it has therefore become even more important that the metal conductors that form the interconnections between devices as well as between circuits in a semiconductor have low resistivity for high signal propagation. Copper is often preferred for its low resistivity, as well as for resistance to electro-migration and stress voiding properties.
On the other hand, considerable attention has focused on the replacement of silicon dioxide with new materials, particular material having lower dielectric constants, since both capacity delays and power consumption depend on the dielectric constant of insulator. Accordingly, circuit performance enhancement has been sought by combining copper conductors with low dielectric constant insulators (k less than approximately 4).
More recently, in order to further improve device performance, researchers have sought to apply dielectric materials with lower dielectric constant than the conventional CVD deposited silicate glasses such as silicon oxide, PSG (phosphosilicate glass) and BPSG (borophosphosilicate glass). Various organic insulator such as parylene, fluorinated polyimides and arylene ether polymers, have been successfully used as low dielectric constant (low-k) replacements for silicon oxide. Porous silica based materials such as siloxanes, silsequioxanes, aerogels, and xerogels have also been implemented as ILD (inter layer dielectric) and IMD (inter-metal dielectric) layers.
However, the spin on dielectric (SOD) materials, like the SOGs and polyimides are extremely sensitive to the methods and conditions by which they are dried and cured after application. Not only are the resultant electrical characteristics of the dielectric layer affected by the drying and curing regimen, but also the physical properties including stress, mechanical strength and physical and chemical durability are affected as well. As shown in FIG. 1, interconnect system is manufactured on conventional low-k IMD system using conventional dual damascene process. The soft SOD layer 112 on a semiconductor structure 110, is adjacent to multitude of conductor contacts 114 and interconnect 115, which is porous dielectric and has weak mechanical strength. However, there are some problems, such as via deformation and structure distortion, happening due to the softness characteristic of the low-k SOD layer.